<!-- HTML header for doxygen 1.8.13-->
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
<meta http-equiv="X-UA-Compatible" content="IE=9"/>
<meta name="generator" content="Doxygen 1.8.13"/>
<meta name="viewport" content="width=device-width, initial-scale=1"/>
<title>MTB CAT1 Peripheral driver library: cy_stc_smif_mem_device_cfg_t Struct Reference</title>
<link href="tabs.css" rel="stylesheet" type="text/css"/>
<script type="text/javascript" src="jquery.js"></script>
<script type="text/javascript" src="dynsections.js"></script>
<link href="navtree.css" rel="stylesheet" type="text/css"/>
<script type="text/javascript" src="resize.js"></script>
<script type="text/javascript" src="navtreedata.js"></script>
<script type="text/javascript" src="navtree.js"></script>
<script type="text/javascript">
  $(document).ready(initResizable);
</script>
<link href="search/search.css" rel="stylesheet" type="text/css"/>
<script type="text/javascript" src="search/searchdata.js"></script>
<script type="text/javascript" src="search/search.js"></script>
<link href="doxygen_style.css" rel="stylesheet" type="text/css" />
</head>
<body>
<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
<div id="titlearea">
<table cellspacing="0" cellpadding="0">
 <tbody>
 <tr style="height: 56px;">
  <td id="projectlogo"><a href="http://www.cypress.com/"><img alt="Logo" src="IFXCYP_one-line.png"/></a></td>
  <td id="projectalign" style="padding-left: 0.5em;">
   <div id="projectname">MTB CAT1 Peripheral driver library</div>
  </td>
 </tr>
 </tbody>
</table>
</div>
<!-- end header part -->
<!-- Generated by Doxygen 1.8.13 -->
<script type="text/javascript">
var searchBox = new SearchBox("searchBox", "search",false,'Search');
</script>
<script type="text/javascript" src="menudata.js"></script>
<script type="text/javascript" src="menu.js"></script>
<script type="text/javascript">
$(function() {
  initMenu('',true,false,'search.php','Search');
  $(document).ready(function() { init_search(); });
});
</script>
<div id="main-nav"></div>
</div><!-- top -->
<div id="side-nav" class="ui-resizable side-nav-resizable">
  <div id="nav-tree">
    <div id="nav-tree-contents">
      <div id="nav-sync" class="sync"></div>
    </div>
  </div>
  <div id="splitbar" style="-moz-user-select:none;" 
       class="ui-resizable-handle">
  </div>
</div>
<script type="text/javascript">
$(document).ready(function(){initNavTree('structcy__stc__smif__mem__device__cfg__t.html','');});
</script>
<div id="doc-content">
<!-- window showing the filter options -->
<div id="MSearchSelectWindow"
     onmouseover="return searchBox.OnSearchSelectShow()"
     onmouseout="return searchBox.OnSearchSelectHide()"
     onkeydown="return searchBox.OnSearchSelectKey(event)">
</div>

<!-- iframe showing the search results (closed by default) -->
<div id="MSearchResultsWindow">
<iframe src="javascript:void(0)" frameborder="0" 
        name="MSearchResults" id="MSearchResults">
</iframe>
</div>

<div class="header">
  <div class="summary">
<a href="#pub-attribs">Data Fields</a>  </div>
  <div class="headertitle">
<div class="title">cy_stc_smif_mem_device_cfg_t Struct Reference<div class="ingroups"><a class="el" href="group__group__smif.html">SMIF         (Serial Memory Interface)</a> &raquo; <a class="el" href="group__group__smif__data__structures.html">Data Structures</a> &raquo; <a class="el" href="group__group__smif__data__structures__memslot.html">SMIF Memory Description Structures</a></div></div>  </div>
</div><!--header-->
<div class="contents">
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<div class="textblock"><p>This configuration structure of the SMIF memory device is used to store device-specific parameters. </p>
<p>These parameters are used to set up the memory mode initialization and the memory API. </p>
</div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a35330244a98f847507496b3f5cbff5aa"><td class="memItemLeft" align="right" valign="top"><a id="a35330244a98f847507496b3f5cbff5aa"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__smif__mem__device__cfg__t.html#a35330244a98f847507496b3f5cbff5aa">numOfAddrBytes</a></td></tr>
<tr class="memdesc:a35330244a98f847507496b3f5cbff5aa"><td class="mdescLeft">&#160;</td><td class="mdescRight">This specifies the number of address bytes used by the memory slave device, valid values 1-4. <br /></td></tr>
<tr class="separator:a35330244a98f847507496b3f5cbff5aa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6dabae268837d0cffde9c25b4efe455d"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__smif__mem__device__cfg__t.html#a6dabae268837d0cffde9c25b4efe455d">memSize</a></td></tr>
<tr class="memdesc:a6dabae268837d0cffde9c25b4efe455d"><td class="mdescLeft">&#160;</td><td class="mdescRight">The memory size: For densities of 2 gigabits or less - the size in bytes; For densities 4 gigabits and above - bit-31 is set to 1b to define that this memory is 4 gigabits and above; and other 30:0 bits define N where the density is computed as 2^N bytes.  <a href="#a6dabae268837d0cffde9c25b4efe455d">More...</a><br /></td></tr>
<tr class="separator:a6dabae268837d0cffde9c25b4efe455d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acbffaff900e449871089a11dea0ad752"><td class="memItemLeft" align="right" valign="top"><a id="acbffaff900e449871089a11dea0ad752"></a>
<a class="el" href="structcy__stc__smif__mem__cmd__t.html">cy_stc_smif_mem_cmd_t</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__smif__mem__device__cfg__t.html#acbffaff900e449871089a11dea0ad752">readCmd</a></td></tr>
<tr class="memdesc:acbffaff900e449871089a11dea0ad752"><td class="mdescLeft">&#160;</td><td class="mdescRight">This specifies the Read command. <br /></td></tr>
<tr class="separator:acbffaff900e449871089a11dea0ad752"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a456a87e11eb3e32c7211b547d49fb747"><td class="memItemLeft" align="right" valign="top"><a id="a456a87e11eb3e32c7211b547d49fb747"></a>
<a class="el" href="structcy__stc__smif__mem__cmd__t.html">cy_stc_smif_mem_cmd_t</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__smif__mem__device__cfg__t.html#a456a87e11eb3e32c7211b547d49fb747">writeEnCmd</a></td></tr>
<tr class="memdesc:a456a87e11eb3e32c7211b547d49fb747"><td class="mdescLeft">&#160;</td><td class="mdescRight">This specifies the Write Enable command. <br /></td></tr>
<tr class="separator:a456a87e11eb3e32c7211b547d49fb747"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4e784af10fe9c014e4303990a5fa8171"><td class="memItemLeft" align="right" valign="top"><a id="a4e784af10fe9c014e4303990a5fa8171"></a>
<a class="el" href="structcy__stc__smif__mem__cmd__t.html">cy_stc_smif_mem_cmd_t</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__smif__mem__device__cfg__t.html#a4e784af10fe9c014e4303990a5fa8171">writeDisCmd</a></td></tr>
<tr class="memdesc:a4e784af10fe9c014e4303990a5fa8171"><td class="mdescLeft">&#160;</td><td class="mdescRight">This specifies the Write Disable command. <br /></td></tr>
<tr class="separator:a4e784af10fe9c014e4303990a5fa8171"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4347b12d2f61a36f2ee4c62bbd756cb5"><td class="memItemLeft" align="right" valign="top"><a id="a4347b12d2f61a36f2ee4c62bbd756cb5"></a>
<a class="el" href="structcy__stc__smif__mem__cmd__t.html">cy_stc_smif_mem_cmd_t</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__smif__mem__device__cfg__t.html#a4347b12d2f61a36f2ee4c62bbd756cb5">eraseCmd</a></td></tr>
<tr class="memdesc:a4347b12d2f61a36f2ee4c62bbd756cb5"><td class="mdescLeft">&#160;</td><td class="mdescRight">This specifies the Erase command. <br /></td></tr>
<tr class="separator:a4347b12d2f61a36f2ee4c62bbd756cb5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad70fca359cefe58ae57c88e70f01d97f"><td class="memItemLeft" align="right" valign="top"><a id="ad70fca359cefe58ae57c88e70f01d97f"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__smif__mem__device__cfg__t.html#ad70fca359cefe58ae57c88e70f01d97f">eraseSize</a></td></tr>
<tr class="memdesc:ad70fca359cefe58ae57c88e70f01d97f"><td class="mdescLeft">&#160;</td><td class="mdescRight">This specifies the sector size of each Erase. <br /></td></tr>
<tr class="separator:ad70fca359cefe58ae57c88e70f01d97f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0c872a037feadc10eadd39dc2fd4e93a"><td class="memItemLeft" align="right" valign="top"><a id="a0c872a037feadc10eadd39dc2fd4e93a"></a>
<a class="el" href="structcy__stc__smif__mem__cmd__t.html">cy_stc_smif_mem_cmd_t</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__smif__mem__device__cfg__t.html#a0c872a037feadc10eadd39dc2fd4e93a">chipEraseCmd</a></td></tr>
<tr class="memdesc:a0c872a037feadc10eadd39dc2fd4e93a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This specifies the Chip Erase command. <br /></td></tr>
<tr class="separator:a0c872a037feadc10eadd39dc2fd4e93a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2b0704e5bdb427719203b8f3d175d219"><td class="memItemLeft" align="right" valign="top"><a id="a2b0704e5bdb427719203b8f3d175d219"></a>
<a class="el" href="structcy__stc__smif__mem__cmd__t.html">cy_stc_smif_mem_cmd_t</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__smif__mem__device__cfg__t.html#a2b0704e5bdb427719203b8f3d175d219">programCmd</a></td></tr>
<tr class="memdesc:a2b0704e5bdb427719203b8f3d175d219"><td class="mdescLeft">&#160;</td><td class="mdescRight">This specifies the Program command. <br /></td></tr>
<tr class="separator:a2b0704e5bdb427719203b8f3d175d219"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8666d1b28383b0e87d4efecd3ac69885"><td class="memItemLeft" align="right" valign="top"><a id="a8666d1b28383b0e87d4efecd3ac69885"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__smif__mem__device__cfg__t.html#a8666d1b28383b0e87d4efecd3ac69885">programSize</a></td></tr>
<tr class="memdesc:a8666d1b28383b0e87d4efecd3ac69885"><td class="mdescLeft">&#160;</td><td class="mdescRight">This specifies the page size for programming. <br /></td></tr>
<tr class="separator:a8666d1b28383b0e87d4efecd3ac69885"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad185b6e5751a2536c004fca1f2325d2c"><td class="memItemLeft" align="right" valign="top"><a id="ad185b6e5751a2536c004fca1f2325d2c"></a>
<a class="el" href="structcy__stc__smif__mem__cmd__t.html">cy_stc_smif_mem_cmd_t</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__smif__mem__device__cfg__t.html#ad185b6e5751a2536c004fca1f2325d2c">readStsRegWipCmd</a></td></tr>
<tr class="memdesc:ad185b6e5751a2536c004fca1f2325d2c"><td class="mdescLeft">&#160;</td><td class="mdescRight">This specifies the command to read the WIP-containing status register. <br /></td></tr>
<tr class="separator:ad185b6e5751a2536c004fca1f2325d2c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a260276b2b1b68a4aa279cff988758121"><td class="memItemLeft" align="right" valign="top"><a id="a260276b2b1b68a4aa279cff988758121"></a>
<a class="el" href="structcy__stc__smif__mem__cmd__t.html">cy_stc_smif_mem_cmd_t</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__smif__mem__device__cfg__t.html#a260276b2b1b68a4aa279cff988758121">readStsRegQeCmd</a></td></tr>
<tr class="memdesc:a260276b2b1b68a4aa279cff988758121"><td class="mdescLeft">&#160;</td><td class="mdescRight">This specifies the command to read the QE-containing status register. <br /></td></tr>
<tr class="separator:a260276b2b1b68a4aa279cff988758121"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad4c73ef9b9a7932c2832347c4c268ffa"><td class="memItemLeft" align="right" valign="top"><a id="ad4c73ef9b9a7932c2832347c4c268ffa"></a>
<a class="el" href="structcy__stc__smif__mem__cmd__t.html">cy_stc_smif_mem_cmd_t</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__smif__mem__device__cfg__t.html#ad4c73ef9b9a7932c2832347c4c268ffa">writeStsRegQeCmd</a></td></tr>
<tr class="memdesc:ad4c73ef9b9a7932c2832347c4c268ffa"><td class="mdescLeft">&#160;</td><td class="mdescRight">This specifies the command to write into the QE-containing status register. <br /></td></tr>
<tr class="separator:ad4c73ef9b9a7932c2832347c4c268ffa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5126d2926b18f7bddf7861165957a041"><td class="memItemLeft" align="right" valign="top"><a id="a5126d2926b18f7bddf7861165957a041"></a>
<a class="el" href="structcy__stc__smif__mem__cmd__t.html">cy_stc_smif_mem_cmd_t</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__smif__mem__device__cfg__t.html#a5126d2926b18f7bddf7861165957a041">readSfdpCmd</a></td></tr>
<tr class="memdesc:a5126d2926b18f7bddf7861165957a041"><td class="mdescLeft">&#160;</td><td class="mdescRight">This specifies the read SFDP command. <br /></td></tr>
<tr class="separator:a5126d2926b18f7bddf7861165957a041"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a386fbd008f608cf037756c486cb902ab"><td class="memItemLeft" align="right" valign="top"><a id="a386fbd008f608cf037756c486cb902ab"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__smif__mem__device__cfg__t.html#a386fbd008f608cf037756c486cb902ab">stsRegBusyMask</a></td></tr>
<tr class="memdesc:a386fbd008f608cf037756c486cb902ab"><td class="mdescLeft">&#160;</td><td class="mdescRight">The Busy mask for the status registers. <br /></td></tr>
<tr class="separator:a386fbd008f608cf037756c486cb902ab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a94531399701237a6c42b7ae8098f9c83"><td class="memItemLeft" align="right" valign="top"><a id="a94531399701237a6c42b7ae8098f9c83"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__smif__mem__device__cfg__t.html#a94531399701237a6c42b7ae8098f9c83">stsRegQuadEnableMask</a></td></tr>
<tr class="memdesc:a94531399701237a6c42b7ae8098f9c83"><td class="mdescLeft">&#160;</td><td class="mdescRight">The QE mask for the status registers. <br /></td></tr>
<tr class="separator:a94531399701237a6c42b7ae8098f9c83"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a04a86cf0c364f59439d81470051f216e"><td class="memItemLeft" align="right" valign="top"><a id="a04a86cf0c364f59439d81470051f216e"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__smif__mem__device__cfg__t.html#a04a86cf0c364f59439d81470051f216e">eraseTime</a></td></tr>
<tr class="memdesc:a04a86cf0c364f59439d81470051f216e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Max time for erase type 1 cycle time in ms. <br /></td></tr>
<tr class="separator:a04a86cf0c364f59439d81470051f216e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:affa18792a98acafd3e86b5fafd6fc59c"><td class="memItemLeft" align="right" valign="top"><a id="affa18792a98acafd3e86b5fafd6fc59c"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__smif__mem__device__cfg__t.html#affa18792a98acafd3e86b5fafd6fc59c">chipEraseTime</a></td></tr>
<tr class="memdesc:affa18792a98acafd3e86b5fafd6fc59c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Max time for chip erase cycle time in ms. <br /></td></tr>
<tr class="separator:affa18792a98acafd3e86b5fafd6fc59c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5156e88b285cfe78f4ff4e42194a70c0"><td class="memItemLeft" align="right" valign="top"><a id="a5156e88b285cfe78f4ff4e42194a70c0"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__smif__mem__device__cfg__t.html#a5156e88b285cfe78f4ff4e42194a70c0">programTime</a></td></tr>
<tr class="memdesc:a5156e88b285cfe78f4ff4e42194a70c0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Max time for page program cycle time in us. <br /></td></tr>
<tr class="separator:a5156e88b285cfe78f4ff4e42194a70c0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af699412addf5631fb6e2d61ece8a89f0"><td class="memItemLeft" align="right" valign="top"><a id="af699412addf5631fb6e2d61ece8a89f0"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__smif__mem__device__cfg__t.html#af699412addf5631fb6e2d61ece8a89f0">hybridRegionCount</a></td></tr>
<tr class="memdesc:af699412addf5631fb6e2d61ece8a89f0"><td class="mdescLeft">&#160;</td><td class="mdescRight">This specifies the number of regions for memory with hybrid sectors. <br /></td></tr>
<tr class="separator:af699412addf5631fb6e2d61ece8a89f0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a989bd3b0d57035f44bd936d185afb7bf"><td class="memItemLeft" align="right" valign="top"><a id="a989bd3b0d57035f44bd936d185afb7bf"></a>
<a class="el" href="structcy__stc__smif__hybrid__region__info__t.html">cy_stc_smif_hybrid_region_info_t</a> **&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__smif__mem__device__cfg__t.html#a989bd3b0d57035f44bd936d185afb7bf">hybridRegionInfo</a></td></tr>
<tr class="memdesc:a989bd3b0d57035f44bd936d185afb7bf"><td class="mdescLeft">&#160;</td><td class="mdescRight">This specifies data for memory with hybrid sectors. <br /></td></tr>
<tr class="separator:a989bd3b0d57035f44bd936d185afb7bf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1c383f7341855294fda5cc5d03b7f270"><td class="memItemLeft" align="right" valign="top"><a id="a1c383f7341855294fda5cc5d03b7f270"></a>
<a class="el" href="structcy__stc__smif__mem__cmd__t.html">cy_stc_smif_mem_cmd_t</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__smif__mem__device__cfg__t.html#a1c383f7341855294fda5cc5d03b7f270">readLatencyCmd</a></td></tr>
<tr class="memdesc:a1c383f7341855294fda5cc5d03b7f270"><td class="mdescLeft">&#160;</td><td class="mdescRight">This specifies the command to read variable latency cycles configuration register. <br /></td></tr>
<tr class="separator:a1c383f7341855294fda5cc5d03b7f270"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aeaa8b36aacfa7b39dcfbbbe042c832a8"><td class="memItemLeft" align="right" valign="top"><a id="aeaa8b36aacfa7b39dcfbbbe042c832a8"></a>
<a class="el" href="structcy__stc__smif__mem__cmd__t.html">cy_stc_smif_mem_cmd_t</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__smif__mem__device__cfg__t.html#aeaa8b36aacfa7b39dcfbbbe042c832a8">writeLatencyCmd</a></td></tr>
<tr class="memdesc:aeaa8b36aacfa7b39dcfbbbe042c832a8"><td class="mdescLeft">&#160;</td><td class="mdescRight">This specifies the command to write variable latency cycles configuration register. <br /></td></tr>
<tr class="separator:aeaa8b36aacfa7b39dcfbbbe042c832a8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2bbe834f1ccfb409c369851d0b5be848"><td class="memItemLeft" align="right" valign="top"><a id="a2bbe834f1ccfb409c369851d0b5be848"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__smif__mem__device__cfg__t.html#a2bbe834f1ccfb409c369851d0b5be848">latencyCyclesRegAddr</a></td></tr>
<tr class="memdesc:a2bbe834f1ccfb409c369851d0b5be848"><td class="mdescLeft">&#160;</td><td class="mdescRight">This specifies the address for variable latency cycle address. <br /></td></tr>
<tr class="separator:a2bbe834f1ccfb409c369851d0b5be848"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af668180d0dac7778ba607ec4bc3ebafe"><td class="memItemLeft" align="right" valign="top"><a id="af668180d0dac7778ba607ec4bc3ebafe"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__smif__mem__device__cfg__t.html#af668180d0dac7778ba607ec4bc3ebafe">latencyCyclesMask</a></td></tr>
<tr class="memdesc:af668180d0dac7778ba607ec4bc3ebafe"><td class="mdescLeft">&#160;</td><td class="mdescRight">This specifies variable latency cycles Mask. <br /></td></tr>
<tr class="separator:af668180d0dac7778ba607ec4bc3ebafe"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Field Documentation</h2>
<a id="a6dabae268837d0cffde9c25b4efe455d"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a6dabae268837d0cffde9c25b4efe455d">&#9670;&nbsp;</a></span>memSize</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">uint32_t cy_stc_smif_mem_device_cfg_t::memSize</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>The memory size: For densities of 2 gigabits or less - the size in bytes; For densities 4 gigabits and above - bit-31 is set to 1b to define that this memory is 4 gigabits and above; and other 30:0 bits define N where the density is computed as 2^N bytes. </p>
<p>For example, 0x80000021 corresponds to 2^30 = 1 gigabyte. </p>

</div>
</div>
</div><!-- contents -->
</div><!-- doc-content -->
<!-- start footer part
<div id="nav-path" class="navpath">
    <ul>
        <li class="footer">
            Generated for <b>MTB CAT1 Peripheral driver library</b> by <b>Cypress Semiconductor Corporation</b>.
            All rights reserved.
        </li>
    </ul>
</div>
-->
</body>
</html>
